Darlington amplifiers are configured to increase amplification by using the gain of multiple transistors to amplify an input signal. FIG. 1 illustrates one configuration of a prior art Darlington amplifier 10. One prior art Darlington amplifier 10 includes a pair of transistors (referred to generically as elements 12 and specifically to a particular transistor as elements Q1-Q2) and consequently is often referred to as a Darlington pair. In the Darlington amplifier 10, an input signal 14 is received at an input terminal 16 and, in response, the Darlington amplifier 10 compounds the gain of each of the transistors 12 to generate an amplified output signal 18, which is transmitted through an output terminal 20. In the illustrated Darlington amplifier 10, the transistors 12 are bipolar junction transistors (BJTs), which have been built on a silicon type semiconductor substrate (not shown), and each has a base, B, a collector, C, and an emitter, E. Upon receiving the input signal 14 at the base, B, of the first amplifying transistor (Q1), the first amplifying transistor (Q1), amplifies the input signal 14 and generates a first collector current 22 (or IC1) from the collector, C. The emitter, E, of the first transistor, (Q1), is connected to the base, B of the second amplifying transistor (Q2) and, in response to the input signal 14, the second amplifying transistor (Q2), also amplifies the input signal 14 to generate a second collector current 24 (or IC2) from its collector, C. Since the collectors, C, of each of the transistors 12 are connected to one another and to the output terminal 20, each of the transistors 12 amplify the input signal 14 to generate the amplified output signal 18, which is a combination of the first collector current 22 and the second collector current 24.
While the Darlington amplifier 10 has the advantage of compounding the gain of each transistor 12 to substantially increase the gain of amplification, the topology of the Darlington amplifier 10 increases the voltage that must be presented by the amplified output signal 18 at the collectors, C, of the first transistor, (Q1), and the second amplifying transistor (Q2) so that the Darlington amplifier reaches a knee voltage, Vknee and operates in an activation region. This is caused by the base-emitter voltage, VBE2, of the second amplifying transistor (Q2) presenting a positive voltage at the emitter, E, of the first amplifying transistor (Q1).
Referring now to FIGS. 1 and 2, a graph illustrating the total Darlington collector current, Ice_total=IC1+IC2, of the combined or total Darlington pair (the first amplifying transistor Q1 & the second amplifying transistor Q2) current versus the voltage, VCE, across the collector, C, and the emitter, E, for different base currents, IB of the first amplifying transistor (Q1). In the prior art Darlington amplifier 10, the Darlington amplifier 10 operates in the activation region once the first amplifying transistor (Q1) reaches its activation region.
The Darlington amplifier 10 has a cut-off voltage, Vcut, and a saturation current of ISAT, when the Darlington amplifier 10 operates in a saturation region 28. In the prior art Darlington amplifier 10, the Darlington amplifier 10 operates in the activation region once the first amplifying transistor (Q1) reaches its activation region. The amplified output signal 18 may be set at a quiescent operating voltage, VQ, which is the voltage of the amplified output signal 18 when no input signal 16 is provided at the input terminal 16. This quiescent operating voltage, VQ, corresponds to a value of VCEQ. The voltage values of the amplified output signal 18 swing across line 30 as the input signal 14 swings to and from its positive and negative peak values.
If the first amplifying transistor (Q1) were coupled alone in a common emitter configuration, the amplified output signal 18 would need to provide a knee voltage, VCEknee (i.e. the saturation voltage of the first amplifying transistor Q1), in order for the first amplifying transistor (Q1) to operate in the activation region. However, the Darlington amplifier 10 has an elevated knee voltage, Vknee having a voltage value 32 instead. This is because the voltage at the emitter, E, of the first amplifying transistor (Q1) is positively biased at ˜VBE2+IC2*R2. Thus, in order for the first amplifying transistor (Q1) to bias up to the forward active region, the knee voltage Vknee, must be provided at the voltage value 32, which may be approximated as:Vknee˜VCEknee+VBE2+IC2*R2.
In the saturation region 28, the Darlington amplifier 10 has a substantially non-linear response. Accordingly, the increase in the size of the saturation region 28 in the Darlington amplifier 10 substantially decreases the linearity of the amplified output signal 18 since the Darlington amplifier 10 operates non-linearly throughout a greater portion of the voltage swing of the input signal 14.
FIG. 3 is yet another embodiment of a prior art Darlington amplifier 34, which in this case uses three transistors 12 to amplify the input signal 14. The prior art Darlington amplifier 34 has the advantage of compounding the gains of the three transistors 12 to even further amplify the input signal 14. However, since the collector terminals, C, of each of the transistors 12 are all coupled to the output terminal 20 this further exacerbates the increase in the knee voltage Vknee of the Darlington amplifier 34. By connecting each of the collectors, C, to the output terminal 20, the voltage of each of the collectors, C, will follow the swing of the amplified output signal 18. The net effect is to increase a knee voltage Vknee to approximately:Vknee˜VCEsat1+VBE2+VBE3+IC3*R3.
Accordingly, it is desirable to provide a Darlington topology that decreases a knee voltage of a Darlington amplifier thereby increasing the linearity of the Darlington amplifier while still allowing multiple transistors in the Darlington amplifier to amplify an input signal.